(a) Field of the invention:
The present invention relates to a semiconductor device, and more particularly it pertains to an insulated-gate static induction transistor, and also to a semiconductor integrated circuit including the same.
(b) Description of the prior art:
Conventional ordinary field effect transistors of both junction and insulated gate types show saturated drain current vs. drain voltage characteristics, i.e. the drain current becomes saturated with an increase in the drain voltage.
A new type of the field effect transistor, i.e. the static induction transistor, was proposed by one of the present inventors, e.g. in U.S. Pat. application Ser. Nos. 817,052 and 576,541 and in IEEE Trans. on Electron Devices, ED-22, pp. 185-197 April 1975.
The static induction transistor (referred to as SIT here-inbelow) has a distinguishing feature that the drain current keeps growing with an increase in the drain voltage at least in a portion of the main operative state regardless of the gate bias voltage. The static induction transistor has the following advantages over the ordinary field effect transistors (referred to as FET, hereinbelow).
(1) At least in a portion of the main operative state, the region between the source and the drain is not punched through, i.e. there remains a neutral region between the source and the gate which is not depleted, and the product of the series resistance r.sub.s and the true transconductance G.sub.m is less than one to exhibit an unsaturating drain current vs. drain voltage characteristic in a low drain current region.
(2) The unsaturating drain current vs. drain voltage characteristic provides a high input impedance, a low output impedance, a large apparent transconductance g.sub.m and less distortion in the signal transfer.
(3) A large output current can be supplied. Also, a high breakdown voltage can be provided by using a high resistivity layer in a predetermined portion. Thus, a high power element with a large output current and a high breakdown voltage can be provided.
(4) The gate region may have a high impurity concentration, and the dimension of the gate structure can be minimized. Thus, both the parasitic capacitance and the resistance of the gate can be reduced to improve high-frequency and high-speed performance.
(5) The amplification factor can be maintained substantially constant in a very wide gate voltage region and in a very wide drain voltage region from a low drain current region in which the drain current vs. drain voltage characteristic fundamentally follows an exponential formula to a high drain current region in which the drain current vs. drain voltage characteristic becomes substantially linear due to an increase in the voltage drop across the series resistance r.sub.s. This unsaturating drain current region may extend over more than ten orders of magnitude. Thereby, operation with very low distortion is feasible.
(6) The amplification factor can be maintained substantially constant down to a very small drain current region. Thereby, an excellent switching operation can be achieved in a low current and low power consumption state.
(7) Temperature dependency of the drain current may be rendered negative at large drain currents. Thereby, thermal runaway can be prevented. Also, active structures which have almost no temperature dependency can be designed.
(8) The amplification factor can be maintained substantially constant through a very wide temperature range, e.g. over two hundred degrees centrigrade.
(9) High speed switching operation can be performed by narrowing the channel width and decreasing the impurity concentration in the channel so that almost no current is allowed to flow at zero gate bias and that a current is allowed to flow when a forward bias voltage is applied to the gate.
(10) High-speed operation can be enhanced by shortening the source-drain distance so that the transit time of carriers therebetween is reduced.
The high input impedance feature allows direct coupling of the succeeding amplifier stages and the non-requirement for the driving power enhances the integration density in an integrated circuit (IC). Furthermore, the large transconductance together with the unsaturating drain current vs. drain voltage characteristic allows a large fan-out, which is extremely fitted for IC and LSI.
As can be seen from the above, the SIT has excellent features in high power, high voltage, large current low distortion, low noise, low power dissipation and/or high speed operation. Together with its temperature dependence, the SIT has many advantages over the conventional bipolar and field effect transistors. Superiority of the SIT as a discrete active element and as an element in IC has been proved and its utility is being developed in various fields.
However, the developments of the SIT made heretofore are mainly concentrated to junction SITs and depletion mode MOS SITs.
In the conventional insulated-gate (hereinafter referred to as IG) FET of enhancement mode, the length and the width of the channel which is formed with an inversion layer are long and narrow, respectively, so that the drain current is saturated for drain voltages above a certain drain voltage. Furthermore, the potential profile in the channel from the source to the drain is monotonic and has no maximum.